@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
@W: BN132 :"c:\users\test\desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":85:1:85:6|Removing sequential instance cap1298_i2c_u3.data_wr[6] because it is equivalent to instance cap1298_i2c_u3.data_wr[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MT529 :"c:\users\test\desktop\calculator_fpga\calculator_cap1298\source\cap1298_i2c.v":51:1:51:6|Found inferred clock cap1298_top|clk_in which controls 61 sequential elements including cap1298_i2c_u1.cnt_200khz[5:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
